The manufacture of integrated circuits in a semiconductor device involves the formation of a sequence of layers that contain metal wiring. Metal interconnects and vias which form horizontal and vertical connections in the device are separated by insulating layers or inter-level dielectric layers (ILDs) to prevent crosstalk between the metal wiring that can degrade device performance. A popular method of forming an interconnect structure is a dual damascene process in which vias and trenches are filled with metal in the same step to create multi-level, high density metal interconnections needed for advanced high performance integrated circuits. A frequently used approach is a via first process in which a via is formed in a dielectric layer and then a trench is formed above the via. Recent achievements in dual damascene processing include lowering the resistivity of the metal interconnect by switching from aluminum to copper, decreasing the size of the vias and trenches with improved lithographic materials and processes to improve speed and performance, and reducing the dielectric constant (k) of insulators or ILDs by using so-called low k materials to avoid capacitance coupling between the metal interconnects. The expression “low-k” material has evolved to characterize materials with a dielectric constant less than about 3.9. One class of low-k material that have been explored are organic low-k materials, typically having a dielectric constant of about 2.0 to about 3.8, which may offer promise for use as an ILD.
Many of the low k materials, however, have properties that are incompatible with other materials employed to fabricate semiconductor devices or are incompatible with processes employed to fabricate the semiconductor devices. For example, layers formed from low dielectric materials are often structurally compromised by Chemical Mechanical Polishing (CMP) processes through erosion, as well as adsorption of CMP slurry chemicals. Etching processes often produce micro-trenches and rough surfaces in layers formed from materials having low dielectric constants, which is often unsuitable for subsequent photolithography processes. As a result, these materials are problematic to integrate into damascene fabrication processes.
To further reduce the dielectric constant of ILDs, structures have been proposed to incorporate void spaces or “air gaps” using, for example, sacrificial materials, in attempts to obtain dielectric constants closer to that of vacuum. For example, U.S. Pat. No. 6,924,222 shows a composite ILD in which a porous dielectric layer is formed over a sacrificial dielectric layer. The sacrificial dielectric layer is formed from a material that is soluble in supercritical carbon dioxide, examples of which include highly-fluorinated or siloxane-based polymer dielectric materials. The porous dielectric layer material may be a zeolite or polymeric material. Subsequent to other processing treatments such as CMP, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous dielectric layer using supercritical carbon dioxide to thereby leave voids in positions previously occupied by portions of the sacrificial dielectric layer. In this way the composite ILD can provide structural support during formation of the conductive features and also provide load distribution and resistance as forces are applied to adjacent layers, such as during planarization. Only after completion of the processing treatments that may be required or facilitated by the mechanical support provided by completely intact layers are the voids created in the sacrificial layers to further reduce the dielectric constant of the ILD.
One problem with the structure shown in the aforementioned reference is that it is composed of only a single removable sacrificial layer and a single porous dielectric layer. The mechanical integrity of this arrangement can be readily compromised, especially when the lateral distance between the conductive layers is large. In this structure the porous dielectric layer may fracture because of thermal expansion that can distort the dielectric layer during processing.
Accordingly, it would be desirable to provide an interconnect dielectric structure that avoids the use of mechanically fragile low-k materials and which also provides additional structural and mechanical support than is provided by the structure shown in the aforementioned reference.